Physical Design Engineer
Xsight Labs · Ho Chi Minh City, Vietnam ·
- Work mode
- Hybrid
- Category
- Hardware
- Experience
- 3+ years
Performs full RTL-to-GDSII physical implementation of high-performance ASIC/SoC chips on 5nm-and-below nodes at Xsight Labs, covering static timing analysis, power/IR-drop integrity, and DRC/LVS/ERC physical verification, using Synopsys or Cadence flows with Tcl/Python/Perl scripting.
Position Summary:
We are seeking an experienced and detail-oriented Physical Design Engineer to join our Advanced ASIC/SoC Development Team. In this role, you will be responsible for the complete RTL-to-GDSII physical implementation of high-performance, complex digital integrated circuits (ICs) built on advanced technology nodes (e.g., 7nm, 5nm, or below). You will collaborate closely with RTL design, architecture, DFT, and CAD team members to deliver power, performance, and area (PPA) optimized silicon on aggressive timelines.
Responsibilities:
· Design Implementation: Execute physical Design from RTL to GDS on advance technology of 5nm and below
· Timing and Power Integrity Closure: Perform Static Timing Analysis, Ensure Power Integrity and meet IR drop criteria.
· Physical Verification: Close DRC, LVS, ERC, ANT
· Work with global Engineer team to deliver design, ensuring design quality
Requirements
· Education: BS, MS in Electrical Engineering, electronics Engineering.
· Minimum of 3 years of hands-on experience in physical design engineering for complex integrated circuits.
· Proficiency in Synopsys (ICC2, Fusion Compiler, PrimeTime) or Cadence (Innovus, Genus)
· Scripting Languages: Strong skills in Tcl, Python, and Perl.
· Experience with advanced processes.