Physical Design Engineer Backend

You will implement RTL-to-GDS physical designs for performance, power, and area. You will perform floorplanning, power planning, placement, clock-tree synthesis, routing, verification, and GDS delivery. You will resolve physical violations, improve QoR through architectural input, and support DSPs or contractors.

Responsibilities

• Implement RTL-to-GDS physical designs for optimal PPA
• Perform floorplanning, power planning, and hard-macro placement
• Optimize block partitioning for turnaround time and quality
• Perform placement, clock-tree synthesis, and routing optimization
• Check and fix DRC, DFM, IR-drop, and electromigration violations
• Perform LVS and PERC checks and deliver GDS
• Propose architectural changes to improve physical-design QoR
• Support DSPs and contractors within turnaround-time targets

Requirements

• Bachelor's degree or higher in Electrical Engineering or equivalent practical experience
• At least 8 years of experience with EDA tool workflows in a semiconductor environment
• Proficiency with Tcl, Perl, or Python for workflow automation and data visualization
• Extensive experience with physical-design processes and RTL-to-GDS automation tools
• Understanding of die-to-package relationships
• Experience leading physical design
• Experience extracting design parameters, summarizing QoR, and analyzing QoR trends