Lead RTL Design Engineer
Cerebras Systems, Inc. · Sunnyvale, CA ·
- Work mode
- Onsite
- Seniority
- Lead
- Category
- Hardware
- Experience
- 8+ years
Lead RTL Design Engineer driving chip design from functional specification to synthesis, managing ASIC vendors, and debugging silicon-level issues. Core technologies include RTL, Python, TCL, and high-speed interfaces like PCIe and Ethernet.
You will drive chip design from functional specification and microarchitecture through RTL development and synthesis. You will manage an external ASIC vendor, partner with physical design, verification, DFT, software, and systems teams, and debug silicon-level functional, timing, and power issues during bring-up.
Responsibilities
- Drive functional specification, microarchitecture, RTL development, and synthesis
- Manage the external ASIC vendor through the product-development cycle
- Partner with physical design to achieve design closure and PPA goals
- Work with verification and DFT teams to achieve functional and test coverage
- Partner with software and systems teams to optimize product performance and features
- Debug silicon-level functional, timing, and power issues during bring-up
Requirements
- Master’s degree in Computer Science, Electrical Engineering, or equivalent
- Ability to work in a hybrid work environment
- 8–15 years of experience delivering complex, high-performance RTL designs
- Experience with front-end chip integration and third-party IP integration
- Experience in networking, high-performance computing, machine learning, or related fields
- Track record of multiple silicon successes
- Experience collaborating with and managing external vendors
- Experience designing or integrating high-speed I/O
- Knowledge of TCP/IP, RDMA, Ethernet, PCIe, CPU interfaces, and Serdes
- Working knowledge of Python and TCL