Lead Design Engineer

Cadence · PUNE · 2 years ago

Seniority: Lead
Category: Engineering design

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

3++ Year ASIC Design / Verification experience. Required Expertise in PCIe / Storage (ONFI, XSPI, SD/eMMC) Design and Verification domain. Good debug skills and good communication skills.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We’re doing work that matters. Help us solve what others can’t.

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