Junior DV and FPGA Prototyping Engineer
Capgemini ·
- Seniority
- Junior
- Category
- Hardware
- Company size
- 1000+
A junior design verification and FPGA prototyping role at Capgemini Engineering in Kyiv: modeling image/audio processing algorithms in Python, implementing RTL in SystemVerilog, building FPGA debug environments on a Zybo Z7 board, and developing SV-based and UVM verification environments.