Implementation Timing / STA Design Engineer
Qualcomm · San Diego, California, United States of America ·
- Work mode
- Onsite
- Category
- Engineering design
- Experience
- 2+ years
Company:
Qualcomm Technologies, Inc.Job Area:
Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.
Qualcomm’s SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis, STA, and timing closure for premium-tier chips. This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm nodes across mobile, AI, and automotive sectors. Candidates should have at least 2 years of experience and be proficient with tools such as Primetime, Fishtail/TCM. Scripting skills in Tcl, Perl, or Python are also desirable.
Principal Duties and Responsibilities
- Develop constraints for physical power-aware synthesis, setup for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis.
- Collaborate closely with RTL design and physical design teams to identify timing requirements and bottlenecks.
- Generate/review, and validate clock domain crossing and design constraints to achieve timing closure of complex SoC cores.
- Review and integrate HM constraints into SoC and ensure correlation between HM and SoC timing.
- Analyze timing across modes and corners, understand concepts like path pessimism and margins.
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
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Pay range and Other Compensation & Benefits:
$145,600.00 - $218,400.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.