IC Logic Design Engineer (STA)

Base: Center of Singapore

Key Responsibilities:

• Perform logic synthesis, LEC, ECO implementation, and quality control throughout the IC development process.
• Work closely with front-end design teams to develop and refine timing constraints and drive timely timing closure.
• Execute full-chip Static Timing Analysis (STA) and ensure the quality and accuracy of timing constraints.
• Collaborate with back-end design teams to complete timing analysis and sign-off.

Requirements:

• Bachelor’s degree or above in Computer Engineering, Electrical/Electronic Engineering, Communications Engineering, or a related field.
• 8+ years of relevant IC design industry experience.
• Strong knowledge of SDC and hands-on experience with Design Compiler (DC), Formality, and PrimeTime (PT).
• Solid Tcl scripting skills.
• Strong understanding of logic synthesis, STA, timing constraints, and timing closure.

EA License: R1987104