High Speed IO Validation Engineer

NVIDIA is widely considered to be one of the world’s most desirable employers in the technology field. We have some of the most forward-thinking and hardworking people in the world working for us. The NVIDIA Silicon Co-Design Group is seeking a versatile engineer to join our High Speed SERDES IO electrical validation team. Your bench is where silicon meets the signal — where every link train, jitter sweep, eye diagram, and protocol corner gets exercised before the part ships. You drive characterization and debug for IO interconnects across silicon, board, firmware, and driver — designing tests that anticipate rack-scale deployment so marginality surfaces at die-and-board scale, never in a rack. Your decisions show up in link margin, BER, power per lane, and the go/no-go calls that gate samples and production.

This role focuses on industry-leading high-speed interconnects such as PCIe, USB3, Ethernet, and UFS. You will perform bring-up and electrical validation with a strong emphasis on quality, stability, and efficiency. Additionally, you will leverage AI-assisted workflows, automation, and advanced analytics to enhance validation quality, accelerate root cause analysis, and improve engineering efficiency. This position offers the opportunity to make a significant impact in a dynamic, technology-driven environment influencing product lines that span artificial intelligence, consumer graphics, self-driving cars, and more.

• Execute electrical validation for PCIe, Ethernet, USB3, and UFS interfaces for NVIDIA GPUs, CPUs, and SOCs, ensuring adherence to signal integrity standards.

• Engage with cross-functional engineering teams to facilitate the design and development process, leveraging your knowledge of firmware/driver interactions and circuit design.

• Analyze complex HSIO bugs by applying strong debugging techniques and collaborating with various teams for rapid resolution.

• Diagnose issues and validate high-speed interfaces using modern lab equipment, including DSOs and BERT, with expert-level proficiency.

• Develop and apply test/debug programs using scripting languages (such as Perl and Python) to perform stress and failure analysis on high-speed interfaces.

• Innovate methodologies that leverage AI-assisted workflows and data-driven analytics to enhance debugging efficiency and improve validation quality.

• BS or MS in Electronics Engineering (or equivalent experience) with at least 3 years of relevant experience.

• Deep high-speed/SERDES electrical validation and tuning experience, with strong SI and PI fundamentals — S-parameters, eye diagrams, channel margin, crosstalk, return loss, PDN noise, jitter decomposition — and validation experience across silicon and platform boundaries (CoWoS/interposer/substrate, board), translating rack-environment effects into silicon/board characterization.

• Expert-level proficiency in electrical validation of PCIe (or similar) protocols, hands-on with lab equipment (DSOs, BERT, protocol analyzers), and scripting skills (Perl, Python) for developing test/debug programs.

• Proven experience in building AI solutions specifically in the context of electrical and silicon validation, including designing and implementing AI-assisted workflows and automation frameworks to enhance engineering productivity and validation quality.

If you are energized by challenging problems, real ownership, deep work, and AI-enabled engineering at scale, we’d love to talk to you.

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