Hardware Engineering Internship 2027
Cambridge, UK | Full-time | Fixed-term, 10–12 weeks | Hybrid
Salary: £30,000–£35,000 per annum, depending on experience, paid pro rata for the internship duration.
About us
Riverlane’s mission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science, to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry’s defining technical challenge, such breakthroughs can never be achieved. Riverlane is the world leader in QEC technology. QEC is a complex problem that requires a range of skills, talent and passion.
Having raised more than $125M in funding to date to accelerate our cutting-edge R&D in quantum error correction (QEC), Riverlane partners with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast.
About the role
Our full-time summer internships give current students in technical fields the opportunity to apply their skills and expertise in an industrial setting.
You will join us at our head office in Cambridge, UK, for 10 to 12 weeks, working alongside talented software and hardware engineers, mathematicians, quantum information theorists and physicists who are experts in their fields.
You will have a dedicated supervisor and work on a project designed to make the best use of your existing skills while developing your knowledge of quantum computing and quantum error correction. We will support you in producing a meaningful piece of work that you can be proud of by the end of your internship.
Previous interns have committed code to industry-standard open-source compilers, co-authored research papers and led the design of new software tools.
What you will do
- Collaborate with experienced hardware and software engineers to investigate and evaluate architectural optimisations
- Enhance the decoder’s architecture to improve its flexibility and processing speed
- Explore different design approaches and evaluate their potential benefits
- Contribute to design decisions involving space and time trade-offs, balancing functionality, resource use and performance
- Communicate your work clearly through technical discussions, presentations and written documentation
- Develop your understanding of FPGA development, quantum computing and quantum error correction
What we need
- You must be a current student at the time of application, either:
- In the second or a later year of a Bachelor’s degree
- Partway through a Master’s degree
- Partway through a PhD
- You must be studying Computer Science, Electronic Engineering, Physics, Mathematics or another related technical subject
- A solid understanding of low-level computer architecture
- Excellent critical-thinking and problem-solving skills
- Strong written and verbal communication skills
- The ability to take initiative and work effectively as part of a team
- A willingness to learn about FPGA development, quantum computing and quantum error correction
- Availability to work full-time for 10 to 12 weeks
Even better if…
- You have experience with RTL development for FPGA or ASIC systems
- You are familiar or interested in quantum computing
- You understand optimisation concepts and performance trade-offs
- You have some knowledge of networking principles
- You have experience using version control, testing or debugging tools
Important notes
- PhD students may need to temporarily step away from their PhD to complete the internship. This may affect their right-to-work status, and applicants should check their individual circumstances
- You must be available to work full-time for 10 to 12 weeks during the summer vacation period
- You will be required to sign an agreement assigning ownership of any intellectual property produced during your internship to Riverlane
- Internships are based at our head office in Cambridge, UK
How to apply
Please upload a CV and covering letter here. Your CV should include the grades that you have so far received in your degree(s). The covering letter should explain why you are applying for the internship and what skills and experience you can bring to the role.
Deadline
Please submit your application by Friday 6th November. Interviews will be held in Cambridge (or virtually if required).
What can you expect from us
Alongside a competitive salary, we offer private medical insurance, a health cash plan and life assurance, as well many other benefits.
You can also expect a diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics and maths) and over 25 different nationalities.
If you have any queries, please contact jobs@riverlane.com. Please do not send your applications to this email address, all applications should be submitted via our careers page.
Everyone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity.
Women and other underrepresented groups may be less likely to apply for a role unless they meet all or nearly all of the requirements. If this applies to you, we still encourage you to apply - you may be a great fit, even if you don’t meet every single qualification. We’d love to hear from you.
If you need any adjustments made to the application or selection process so you can do your best, please let us know. We will be happy to help.
GDPR notice: Riverlane collects and processes personal data in accordance with applicable data protection laws. If you are a European Job Applicant see the privacy notice for further details.