DfT Architect

Design for Test (DfT) Architect

The DfT Architect is responsible for defining and governing the Design-for-Test strategy and architecture for complex SoCs and IPs. The role coordinates across System Architecture, Design, Verification, Physical Design, Product Engineering and Test Engineering disciplines to ensure optimal test quality, test cost and manufacturability.

The DfT Architect translates product requirements into a comprehensive DfT specification and drives implementation of scalable, reusable and innovative DfT solutions. As a recognized technical leader, the architect influences technical direction across projects, develops new methodologies, and mentors engineers and architects within the organization. Based on the NXP role definition for DfT Architect.

Key Responsibilities

DfT Strategy & Architecture

• Define the overall DfT strategy for SoCs and IPs.

• Establish digital, memory and analog DfT architectures.

• Create and maintain the DfT Specification.

• Define testability requirements and acceptance criteria.

• Drive architectural decisions balancing quality, cost, test time and schedule.

• Assess test impact of specification and design changes.

Technical Leadership

• Act as technical lead for DfT implementation teams.

• Drive alignment between architects, designers, verification engineers and product engineers.

• Review designs for compliance with DfT requirements.

• Resolve complex technical issues and architectural trade-offs.

• Lead DfT reviews throughout the product lifecycle.

Test Quality & Production Readiness

• Define test concepts required to achieve target quality levels.

• Guide fault modelling and coverage strategy.

• Support prediction of yield, DPPM, test coverage and test cost.

• Support silicon bring-up, characterization and production ramp.

• Drive root-cause analysis of field and production failures.

Methodology & Innovation

• Develop and deploy new DfT methodologies.

• Drive standardization and reuse across projects and business lines.

• Influence EDA tool roadmaps and automation improvements.

• Participate in internal and external technical working groups.

• Monitor industry trends and introduce best practices.

Competence Development

• Coach DfT engineers and emerging architects.

• Build organizational competence through training and mentoring.

• Contribute to hiring and technical career development.

• Serve as a recognized expert within NXP and externally.

Qualifications

• MSc or PhD in Electrical Engineering, Computer Engineering or related discipline.

Experience

• 15+ years of experience in semiconductor development.

• Proven experience as DfT Architect, Lead Engineer or Technical Lead.

• Track record delivering complex SoC products from concept through production.

Technical Expertise

Strong knowledge of:

• Scan architecture and ATPG / Test compression / JTAG / IEEE1687 / JTAG / IEEE1149.x

• Memory BIST / Logic BIST

• Analog DfT and mixed-signal test

• Fault modelling and coverage analysis / Silicon debug and diagnosis

• Production test development

• Automotive quality methodologies

• RTL design and verification flows

• Modern EDA tools (Synopsys, Cadence, Siemens.

Leadership Competencies

• Strategic thinking

• Systems perspective

• Technical influencing

• Stakeholder management

• Coaching and mentoring

• Change leadership

• Excellent communication skills