Custom Circuit Design (Sr. Staff / Principal)

Responsibilities

● Lead the architecture, design, and optimization of high-performance, low-power standard cells targeting advanced process technologies with a strong focus on Performance, Power, and Area (PPA).

● Design and optimize transistor-level circuits including latches, flip-flops, multiplexers, AOI/OAI, XOR/XNOR, encoders, decoders, level shifters, arithmetic cells, and other complex sequential and combinational logic.

● Architect and develop advanced arithmetic building blocks, including adders, multipliers, integer and floating-point MAC units, for high-performance compute applications.

● Develop schematics using Cadence Virtuoso and perform post-layout validation through parasitic extraction using StarRC or Quantus.

● Perform circuit verification across all PVT corners using HSPICE, PrimeSim XA, or Spectre, ensuring robust functionality, timing, and power performance.

● Drive statistical verification using Monte Carlo methodologies and advanced variation analysis with Solido, Spectre FMC, or equivalent tools.

● Own reliability sign-off activities, including electromigration (EM), IR-drop, self-heating, BTI/HCI aging analysis, while ensuring ESD and latch-up robustness.

● Drive low-power circuit innovations through multi-Vt optimization, leakage reduction, power gating, retention strategies, isolation cells, and power-intent-aware design methodologies.

● Collaborate closely with custom layout teams to optimize layouts for Layout Dependent Effects (LDE), manufacturability, coloring compliance, matching, and pin accessibility.

● Partner with Characterization, Physical Design, STA, CAD, and Product Engineering teams to ensure successful library development, silicon readiness, and production-quality deliverables.

● Drive design methodology improvements, automation initiatives, and technical best practices across the circuit design organization.

● Mentor engineers and provide technical leadership in circuit design, methodology development, and advanced technology enablement.

● Deep understanding of advanced process technologies including FinFET and Gate-All-Around (GAA).

● Extensive experience with circuit simulation tools such as HSPICE, PrimeSim XA, or Spectre.

● Experience with parasitic extraction using StarRC or Quantus.

● Strong knowledge of statistical verification, Monte Carlo analysis, and variation-aware circuit design.

● Experience performing reliability verification including EM, IR-drop, aging, self-heating, and silicon robustness analysis.

● Demonstrated ability to drive complex technical projects from concept throughsilicon.

Preferred Qualifications

● Master's or Ph.D. in Electrical Engineering, Electronics Engineering, or a related discipline.

● Strong understanding of digital circuit architecture, standard cell design, and advanced flip-flop architectures.

● Experience with standard cell characterization using Liberate or PrimeLib, including Liberty (.lib) generation and validation.

● Good understanding of Static Timing Analysis (STA), Liberty timing models, and ASIC sign-off methodologies.

● Familiarity with complete ASIC development flows from circuit design through physical implementation and silicon validation.

● Experience developing automation using Python, Tcl, or Perl.

● Track record of leading technical initiatives and mentoring engineering teams.

● Experience with SRAM peripheral circuit design.

● Knowledge of UPF and power intent methodologies.

● Exposure to layout optimization techniques including LDE, coloring, matching, and pin accessibility.

● Familiarity with silicon bring-up, characterization, and production support.

● Experience driving design methodology improvements and EDA automation.

● Strong technical leadership, mentoring, communication, and cross-functional collaboration skills.

● Passion for innovation and delivering high-quality silicon under aggressive product schedules.

● Background in custom digital CMOS circuit design; standard cell library architecture, design, and optimization; arithmetic circuit design, including adders, multipliers, comparators, and MAC units; low-power circuit design and
optimization; advanced-node technologies including FinFET and GAA; library characterization and timing model development; or cross-functional silicon development in advanced semiconductor environments.

Why Velaura?

Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world.
This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you.

Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment
opportunities to minorities, women, individuals with disabilities, and protected veterans.

Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: [email protected]. This contact
information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.