ATE Solution Test Engineer
Altera Corporation · San Jose, California, United States ·
- Category
- QA
- Experience
- 3+ years
- Visa sponsorship
- Yes
- Company size
- 1000+
- Salary
- USD 118,900 – 172,000 / year
Altera Corporation · San Jose, California, United States ·
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Designs and maintains automated test equipment (ATE) solutions for FPGA chips, focusing on scalable test programs and hardware optimization for production using Teradyne/Advantest platforms.
About Altera
At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
About the Role
The ATE Solution Test Engineer is responsible for delivering best in class ATE test solutions that are scalable, high quality, and aligned to product needs. Our mission is to standardize and simplify methodologies and flows, enabling predictable, fast, and consistent Test Program (TP) releases. In addition, we will deliver test hardware designed & optimized for production across all FPGA products.
Responsibilities:
Develop, validate, and maintain ATE test methods and production test programs for wafer sort and final test using Teradyne and/or Advantest platforms.
Own product test development through the complete product lifecycle—from NPI, silicon bring-up, characterization, qualification, and production ramp to sustaining engineering.
Analyze silicon performance across process, voltage, and temperature (PVT) corners to establish production limits and optimize guardbands.
Drive yield improvement, test time reduction, and defect escape prevention through data-driven analysis and test optimization.
Perform silicon, tester, hardware, and manufacturing debug to resolve complex product issues.
Collaborate with cross-functional teams including Design, DFT, Validation, Reliability, Package Engineering, Manufacturing, and OSAT partners to ensure successful product execution.
Support production releases, manufacturing transfers, and high-volume manufacturing while driving continuous improvements in quality and cost of test.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$118,900 - $172,000 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
#LI-MD1
Minimum Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related engineering discipline.
5+ years of industry experience developing Automated Test Equipment (ATE) test programs using Teradyne and/or Advantest platforms.
5+ years of experience with semiconductor test methodologies, silicon characterization, and production test development for complex semiconductor devices.
5+ years of experience developing and implementing ATE test methods for semiconductor products from characterization through high-volume manufacturing.
5+ years of experience working with Design-for-Test (DFT) architectures, including Scan, MBIST, JTAG, Boundary Scan, and ATPG.
5+ years of experience supporting wafer sort, final test, and semiconductor manufacturing test flows.
5+ years of experience working with production test hardware, including probe cards, load boards, sockets, and related ATE interface hardware.
5+ years of experience analyzing process variation, optimizing test guardbands, and developing production test limits to improve yield and quality.
5+ years of programming or scripting experience using Python, Perl, C++, or similar languages to automate test development, data analysis, or engineering workflows.
5+ years of experience using JMP or equivalent statistical data analysis tools for silicon characterization, yield analysis, and test optimization.
3+ years of experience working in Agile development environments and using version control systems (e.g., Git or equivalent).