ASIC Physical Design, Sr Engineer - 18156

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years turning RTL into silicon that actually works, not just passes checks, but ships, performs, and comes back from the fab without surprises. You know that a floorplan decision made in week two will either save or cost you three weeks at tape-out, and you are the kind of engineer who sees that trade-off clearly and makes the call with confidence. You have lived through enough timing closures to know when a violation is real and when it is noise, and you do not panic when the sign-off checklist grows to 47 items two days before delivery.

Scripting is not a side task for you, it is how you scale yourself. You write Tcl and Python that other engineers can actually read and use, because you have seen what happens when flows are held together by one person's undocumented magic. You do not wait for perfect documentation from the foundry. You read what exists, ask the right questions, and build a methodology that works within the constraints you have. When IR-drop blows up or a clock tree will not converge, you dig in, find the root cause, and fix it in a way that does not break three other things downstream.

What You'll Be Doing

• Own the full RTL-to-GDSII physical implementation flow for memory test-chip blocks and top-level designs, driving synthesis, floorplanning, power planning, placement, CTS, routing, and sign-off closure
• Develop and maintain Back-End implementation and sign-off flows including PnR, STA, PV, IR/EM analysis, and extraction methodologies
• Review and implement foundry sign-off requirements and tape-out checklists, ensuring manufacturing compliance and first-pass silicon success
• Execute timing analysis and closure across multiple PVT corners, optimizing for power, performance, and area
• Drive physical and electrical verification using Synopsys IC Validator, resolving DRC, LVS, ERC, antenna, EM, IR-drop, and signal integrity issues
• Collaborate with Foundry, CAD, Front-End, DFT, STA, and Design teams to resolve implementation challenges and hit project milestones
• Build automation frameworks and scripts in Python, Tcl, and Perl that improve design productivity and flow efficiency

The Impact You Will Have

• Enable successful first-pass silicon for memory test-chip designs by delivering clean, manufacturable GDSII with complete sign-off collateral
• Reduce design cycle time through robust, repeatable Back-End flows that scale across multiple projects and process nodes
• Eliminate late-stage surprises by catching timing, power, and physical issues early and building methodologies that prevent recurrence
• Strengthen foundry partnerships by implementing sign-off requirements correctly and providing feedback that improves design enablement
• Accelerate team productivity by delivering automation that removes manual bottlenecks and makes complex tasks repeatable
• Contribute to Synopsys IP competitiveness by ensuring memory designs meet aggressive performance and power targets on advanced nodes
• Elevate team capability by sharing knowledge, documenting best practices, and building flows others can learn from and extend

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline
• 5+ years of hands-on ASIC physical design experience with proven silicon tape-outs, ideally on advanced process nodes
• Deep expertise across the full RTL-to-GDSII implementation flow including synthesis, floorplanning, power planning, placement, CTS, routing, and sign-off
• Strong proficiency with Synopsys tools including Fusion Compiler or ICC2, PrimeTime, StarRC, and IC Validator
• Solid scripting and automation skills in Tcl, Python, and Perl with a track record of building flows that improve team efficiency
• Experience setting up and maintaining Back-End design and sign-off methodologies including PnR, STA, PV, extraction, and IR/EM analysis
• Ability to interpret and implement foundry sign-off requirements and tape-out checklists to ensure manufacturing readiness

Who You Are

• You can look at a floorplan and immediately see the congestion, power, or timing problems that will surface later, and you address them before they become crises
• When a sign-off violation appears, you dig into the data, trace it to root cause, and fix it in a way that makes sense for the design and the flow
• You write scripts and build flows with the next engineer in mind, clear variable names, comments that explain why, and structure that someone else can extend
• You communicate clearly across disciplines, translating technical issues for front-end designers or CAD engineers without losing the thread
• You stay calm under pressure, especially in the final weeks before tape-out, and you help the team stay focused on what actually matters

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.