ASIC Design Engineer 2

ASIC Design Engineer 2

Organization:

HPE is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use. At Juniper Silicon group, we push the boundaries of what is possible in a piece of silicon die. We build cutting edge networking chips used to build world-class routers and switches.

Bring your passion and there are no boundaries to what you can accomplish here. We are like a start-up in a big company. Year after year, our group builds the most powerful and highest density networking chips.

As part of our fast-paced chip design group, you will become an expert in building high-speed ASICs, from specifications to final netlist. You can pick and choose where you want to work on – design/ verification or timing closure/PD. As you are getting started in your career, we will let you explore your passions here.

Open communications, empowerment, innovation, teamwork and customer success are the foundations of team culture. Thus, you set your own limits for learning, achievements and rewards.

Responsibilities:

• You will start with a functional specification of a module and come up with a detailed micro-architecture specification – do not worry, you will have guidance from our senior engineers on how to go about this if you have not done this before.

• RTL coding – we prefer you know System Verilog and have done several school/intern projects (coding to synthesis) using this language.

• Write functional coverage/SVA (we will teach you how to do this if you haven’t done this before)

• Timing closure – work with PD to identify timing paths and fix timing in RTL to meet the frequency target.

• Debug issues in your block found by verification team.

• Use state-of-the-art EDA tools for various design checks.

Recommended skills

• Bachelor’s degree in Electrical Engineering required, Master’s strongly desired.

• Strong analytical/ problem solving skills.

• Should have taken courses for credit in digital logic design.

• Strong coding skills in Verilog/System Verilog through courses and intern projects

• Knowledge of Computer Architecture/networking protocols/machine learning through graduate level courses is a plus.

• Excellent written and verbal communications skills is good to have.

• Knowledge of Perl/Python is a plus

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.