Analog / Mixed-Signal SerDes Design Engineer - Cork, Ireland
Qualcomm · Cork, Ireland ·
- Work mode
- Onsite
- Category
- Engineering design
- Experience
- 1+ years
Company:
QT Technologies Ireland LimitedJob Area:
Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:
About the role
Qualcomm’s SerDes PHY team is seeking Analog / Mixed-Signal design engineers to join our growing team in Cork, Ireland. The successful candidate will work on analog and mixed-signal integrated circuits for high speed PHY receivers and drivers, VCOs, PLLs, and a range of other custom IP for Qualcomm Mobile, Auto, IoT & Compute SoC products. The primary focus of the work is on low-power and low-voltage mixed-signal design with emphasis on advanced nanometer FinFET and GAA technology nodes.
The successful candidate will both design key circuit blocks and work closely with layout engineers to ensure the layout is fully optimized and complies with best analog layout practices. You will be directly involved in delivering next-generation SerDes and PLL designs for Qualcomm SoCs and will be part of a large analog mixed-signal design team involved in architecture analysis and IP delivery in leading-edge FinFET and GAA process technology nodes at 3nm and below.
The role requires industry experience in transistor-level circuit implementations or highly relevant academic experience in a Masters’ or PhD program focused on full custom analog circuit design using nanometer CMOS technologies. In addition to Analog and Mixed-Signal circuit design expertise, good understanding of device physics, analog circuit custom layout, power distribution networks (PDN), mixed-signal design flow, SoC top-level integration and IC Design Tools are desired.
Responsibilities:
Architecture, design, and development of analog / mixed signal hard macros for the SerDes IP Design team
Perform custom circuit design in the latest FinFET CMOS processes technologies and beyond to support the delivery of SerDes IP
Participate in internal customer requirements discussions.
Create design specifications.
Create behavioural models in Verilog.
Set-up, run and analyse circuit simulations.
Perform quality assurance procedures on developed hard macros.
Deliver hard macros and support customer integration and testing.
Perform silicon characterization analysis and prepare silicon verification reports.
Skills and Experience we would love to see:
Master’s or Ph.D. degree in Science, Engineering, or related field.
A minimum of 3-years of transistor level analog mixed-signal design experience, preferably in high-speed wireline SerDes, PLL, DDR or other high speed applications
Experience in SPICE simulators and schematic capture tools
Experience in designing op-amps, bandgaps, differential amplifiers, VCO, PLL, DLL
Experience in high-speed SerDes block level designs such as transmitters, receivers, high speed VGA, CTLE, CDR, etc.
Understanding of signal integrity in high-speed wireline design is preferred
Scripting to automate circuit design and verification work
Full-custom analog layout techniques and the ability to take a design and do all the layout extract verification and sign-off
Excellent communication skills and ability to contribute strongly within a high-performance team
Minimum Qualifications:
Bachelor's degree in Science, Engineering, or related field.
2+ years ASIC design, verification, or related work experience.
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
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