Analog Design Engineer
ovt · Santa Clara, United States ·
- Category
- Hardware
• Conduct end-to-end design and development of advanced CMOS Image Sensor (CIS) technologies with a focus on transistor-level design, simulation, and verification of analog circuits using Cadence Virtuoso.
• Design analog building blocks such as Analog Static RAM (ASRAM), ensuring support for complex readout formats including Dual Conversion Gain (DCG), Correlated Double Sampling (CDS), Correlated Multiple Sampling (CMS), and 4c2p.
• Perform complete schematic design flow, closely collaborate with layout engineers on device matching, symmetry, shielding, and routing for optimal noise performance and area efficiency.
• Carry out comprehensive post-layout verification, including Parasitic Extraction (PEX), Design Rule Check (DRC), Layout vs. Schematic (LVS), and Physical Electrical Rule Check (PERC) using Calibre.
• Conduct system-level analog simulation and CIS signal chain verification to ensure correct signal propagation from pixel through the entire analog front-end to digital input interface.
• Execute extensive process, voltage and temperature (PVT) and Monte Carlo simulations to evaluate functional robustness, and performance margins.
• Perform IR drop analysis and power integrity verification to ensure reliable power delivery and layout feasibility.
• Utilize Analog FastSPICE (AFS), Empyrean ALPS, and NanoSpice for block-level and full-chain validation under realistic operating scenarios.
• Develop and maintain automation scripts in Python and Perl to streamline simulation flow, including netlist generation, corner sweeping, batch result parsing, and yield analysis. Build scalable toolchains to support multi-corner, multi-mode simulations and regression testing, enhancing design turnaround and validation coverage.
• Collaborate with cross-functional teams with digital design, verification, process, and test to define analog-digital interface specifications, establish timing constraints, support readout calibration algorithms, and debug post-silicon performance issues.
• Participate in design reviews, tapeout signoff, and lab characterization, contributing to silicon bring-up and performance optimization.
• Design analog building blocks such as Analog Static RAM (ASRAM), ensuring support for complex readout formats including Dual Conversion Gain (DCG), Correlated Double Sampling (CDS), Correlated Multiple Sampling (CMS), and 4c2p.
• Perform complete schematic design flow, closely collaborate with layout engineers on device matching, symmetry, shielding, and routing for optimal noise performance and area efficiency.
• Carry out comprehensive post-layout verification, including Parasitic Extraction (PEX), Design Rule Check (DRC), Layout vs. Schematic (LVS), and Physical Electrical Rule Check (PERC) using Calibre.
• Conduct system-level analog simulation and CIS signal chain verification to ensure correct signal propagation from pixel through the entire analog front-end to digital input interface.
• Execute extensive process, voltage and temperature (PVT) and Monte Carlo simulations to evaluate functional robustness, and performance margins.
• Perform IR drop analysis and power integrity verification to ensure reliable power delivery and layout feasibility.
• Utilize Analog FastSPICE (AFS), Empyrean ALPS, and NanoSpice for block-level and full-chain validation under realistic operating scenarios.
• Develop and maintain automation scripts in Python and Perl to streamline simulation flow, including netlist generation, corner sweeping, batch result parsing, and yield analysis. Build scalable toolchains to support multi-corner, multi-mode simulations and regression testing, enhancing design turnaround and validation coverage.
• Collaborate with cross-functional teams with digital design, verification, process, and test to define analog-digital interface specifications, establish timing constraints, support readout calibration algorithms, and debug post-silicon performance issues.
• Participate in design reviews, tapeout signoff, and lab characterization, contributing to silicon bring-up and performance optimization.
Requirements:
Master’s degree in Electrical Engineering, Computer Engineering, or a related field with advanced-level courses work in Analog Integrated Circuit, CMOS Circuit Design, RF Circuits and Systems Design, VLSI system design, and VLSI Signal Processing.
Must possess the following skills:
• Analog circuits using MOS models,
• Operational amplifier and current mirror design,
• Noise analysis and feedback system,
• Evaluation of offset distortion and nonlinearity,
• Functional verification using ModelSim,
• Static timing analysis, power and area estimation,
• Standard-cell based logic and physical synthesis,
• Hardware scheduling and retiming,
• Number representation and digital arithmetic,
• Full analog IC design flow,
• Post-tapeout chip testing and validation,
• VLSI circuit and system design using Verilog,
• Architecture design space exploration,
• Spectrum Analyzer.
• Operational amplifier and current mirror design,
• Noise analysis and feedback system,
• Evaluation of offset distortion and nonlinearity,
• Functional verification using ModelSim,
• Static timing analysis, power and area estimation,
• Standard-cell based logic and physical synthesis,
• Hardware scheduling and retiming,
• Number representation and digital arithmetic,
• Full analog IC design flow,
• Post-tapeout chip testing and validation,
• VLSI circuit and system design using Verilog,
• Architecture design space exploration,
• Spectrum Analyzer.
Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.