3D Stacked Logic Design Engineer

Job Title: 3D Stacked Logic Design Engineer
Office Location: San Jose, CA
Job Type: Full-Time
Work Model: Onsite

Job Summary:

To strengthen leadership in the DRAM-on-Logic era through optimized DRAM die design, we are seeking talent capable of driving the co-design of 3D-stacked DRAM logic dies in close collaboration with U.S.-based customers. This strategic hiring initiative aims to enhance our global competitiveness by fostering deep engagement with key American clients, ensuring that our die design solutions are precisely aligned with their evolving technical requirements and market demands.

Responsibilities:

• Strengthen leadership in the DRAM-on-Logic era through advanced digital IP design for 3D-stacked DRAM.
• Provide digital IP services for 3D-stacked DRAM to enable DRAM-on-Logic system configurations for customers.
• Co-design 3D-stacked DRAM Logic Dies with U.S.-based customers.
• Improve competitiveness through close engagement with customers in the U.S.
• Design high-speed digital IP for 3D-stacked DRAM peripheral circuits and DRAM DFT with U.S.-based customers, covering RTL design to implementation.
• Conduct foundry verification of service-ready IPs and setting up infrastructure for the IP business.
• Deliver services to ensure seamless IP integration in customer design environments.
• Design digital logic blocks for 3D-stacked DRAM peripherals and Design-for-Test (DFT) features.
• Establish close technical engagement with key U.S.-based customers to address immediate 3D-stacked DRAM requirements.
• Establish close technical engagement with foundry partners (e.g., TSMC, Intel) to build digital IP for 3D-stacked DRAM.

Qualifications:

• Bachelor’s degree or higher in Electrical Engineering or a related discipline with 5+ years of relevant experience.
• Development of Digital Logic IP/SoC based on Hardware Description Languages (Verilog, VHDL).
• Experience in RTL design and implementation memory PHY, hard macro IP for high-speed circuit, or high-speed digital IP design.
• Experience with memory controllers.
• Experience in memory Built-in Self-Test (BIST), DRAM Design for Test (DFT) / Design for Debug (DFD).
• Deep understanding of PPA analysis and optimization, and physical design.
• Excellent verbal and written communication in English; ability to present technical concepts to cross functional teams and senior management.

Benefits:

• Top Tier health insurance at no employee cost
• Paid day offs: Paid Time Off, Company Holidays, Parental Leave, Happy Fridays
• 401k Matching
• Flexible Spending Account (FSA) for Health Care & Dependent Care
• Educational reimbursement up to $10,000 per year
• Donation Matching and volunteering opportunities
• Corporate discount programs
• Free Breakfast/Lunch/Dinner provided to employees